Makefile File — Make Build Script

Makefiles define build rules and dependencies for the make build automation tool, originally created by Stuart Feldman at Bell Labs in 1976. A Makefile consists of rules, each with a target, optional prerequisites (dependencies), and a recipe (commands to execute). Make determines which targets need rebuilding based on file modification timestamps, executing only the minimum necessary commands. Makefiles use TAB-indented recipe lines (a notorious requirement), variables for configurable paths and flags, pattern rules for generic build instructions, and automatic variables ($@, $<, $^) for concise rule definitions. Make was designed for compiling C programs but has become a universal task runner — projects in any language use Makefiles for build commands, test execution, deployment scripts, and development workflows. GNU Make is the most widely used implementation, with extensions including conditional logic, functions for text transformation, and include directives for modular organization. Despite the availability of modern build tools, Makefiles remain the standard for C/C++ projects, Linux kernel builds, and as a convenient task runner interface for projects using any build system.